Title :
Design considerations for paralleling bipolar transistors
Author :
Jovanovic, Milan M. ; Lee, Fred C.
Author_Institution :
Department of Electrical Engineering Virginia Polytechnic Institute and State University Blacksburg, Virginia 24061, U.S.A.
fDate :
April 28 1986-1986
Abstract :
A simple design procedure for direct paralleling of bipolar junction transistors (BJTs) is proposed. It is based on the matching of transfer characteri stics (In vs Vnr. ) at low collector voltage. The design procedure further addresses base and coll ectorcircuit´s layout requirements, optimal base-drive conditions, and thermal design requirements for reliable and efficient operation of BJTs inparallel. The influence of a snubber circuit is also discussed. The procedure is verified experimentally by performing dynamic and reverse-bias safe operating area (RBSOA) testings.
Keywords :
Electric breakdown; Junctions; Layout; Snubbers; Switches; Switching circuits; Transistors;
Conference_Titel :
Applied Power Electronics Conference and Exposition, 1986 IEEE
Conference_Location :
New Orleans, Louisiana, USA
DOI :
10.1109/APEC.1986.7073332
