A low-power and cost-effective AES chip design for healthcare devices

Author

Liang, Yunping ; Li, Ye

Author_Institution

Res. Center for Biomed. Inf. Technol., Shenzhen Inst. of Adv. Technol., Shenzhen, China

fYear

2012

fDate

5-7 Jan. 2012

Firstpage

795

Lastpage

798

Abstract

Information security is very important to health information, and Cryptography is the key measure for information security. This paper proposes a low-power and cost-effective implementation of AES (Advanced Encryption Standard) supporting encryption and decryption with 128-bit cipher key. Considering the cost-effective, resource-sharing scheme is employed to reduce the hardware complexity of the cipher and decipher. Considering the low-power, we present a mixed pipelining architecture. The performance is evaluated on SMIC 0.18um CMOS technology and the throughput achieves at 800Mbps with the cost of only 17519 equivalent NAND2 gates, and the power consumption is only 9.7mw.

Keywords

CMOS integrated circuits; cryptography; health care; low-power electronics; microprocessor chips; SMIC CMOS technology; advanced encryption standard; bit rate 800 Mbit/s; cost-effective AES chip design; cryptography; decryption; health information; healthcare devices; information security; low-power AES chip design; power 9.7 mW; size 0.18 mum; word length 128 bit; Cryptography; Hardware design languages; IP networks; Registers; AES; mixed pipelining; resource-sharing;

fLanguage

English

Publisher

ieee

Conference_Titel

Biomedical and Health Informatics (BHI), 2012 IEEE-EMBS International Conference on

Conference_Location

Hong Kong

Print_ISBN

978-1-4577-2176-2

Electronic_ISBN

978-1-4577-2175-5

Type

conf

DOI

10.1109/BHI.2012.6211704

Filename

6211704