A H.264 video decoder with scheme of efficient bandwidth optimization for motion compensation

In this paper, we present a H.264 video decoder design for baseline profile application, with a special emphasis on the motion compensation (MC) bandwidth optimization scheme. The proposed design can achieve real-time H.264 video decoding for D1@30fps at 55 MHz, which is, to a great extent, attributed to the MC bandwidth optimization scheme. Fabricated by SMIC one-poly six-metal 0.13mum CMOS technology, the design occupies 2 x 2 mm silicon area with hardware complexity of 280K gates and 95K bits of local memory, which is better than current implementations published in Kun, et al. (2006).