DocumentCode :
2258747
Title :
Study of nonlinear dynamics of LDPC decoders
Author :
Zheng, Xia ; Lau, Francis C M ; Tse, Chi K. ; Wong, Siu Chung
Author_Institution :
Dept. of Electron. Inf. & Eng., Hong Kong Polytech. Univ., China
Volume :
2
fYear :
2005
fDate :
28 Aug.-2 Sept. 2005
Abstract :
Low-density-parity-check (LDPC) codes have aroused much research interest because of their excellent bit error performance. The behaviour of the iterative LDPC decoders, however, has not been fully investigated at all signal-to-noise ratios (SNRs). By considering the LDPC decoders as high-dimensional nonlinear dynamical systems, we attempt to study the corresponding phase trajectories at different SNR values. By having an in-depth understanding of the decoder behaviour, engineers should be able to design more effective and efficient decoders.
Keywords :
bifurcation; error statistics; iterative decoding; nonlinear dynamical systems; parity check codes; turbo codes; bit error performance; high-dimensional nonlinear dynamical systems; iterative LDPC decoders; low density parity check code; phase trajectory; signal-to-noise ratio; Bifurcation; Bit error rate; Block codes; Convergence; Design engineering; Iterative algorithms; Iterative decoding; Nonlinear dynamical systems; Parity check codes; Signal to noise ratio;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuit Theory and Design, 2005. Proceedings of the 2005 European Conference on
Print_ISBN :
0-7803-9066-0
Type :
conf
DOI :
10.1109/ECCTD.2005.1523017
Filename :
1523017
Link To Document :
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