• DocumentCode
    2258790
  • Title

    Automatic workload generation for system-level exploration based on modified GCC compiler

  • Author

    Kreku, Jari ; Tiensyrjä, Kari ; Vanmeerbeeck, Geert

  • Author_Institution
    VTT Tech. Res. Center of Finland, Oulu, Finland
  • fYear
    2010
  • fDate
    8-12 March 2010
  • Firstpage
    369
  • Lastpage
    374
  • Abstract
    Future embedded system products, e.g. smart hand-held mobile terminals, will accommodate a large number of applications that will partly run sequentially and independently, partly concurrently and interacting on massively parallel computing platforms. Already for systems of moderate complexity, the design space will be huge and its exploration requires that the system architect is able to quickly evaluate the performances of candidate architectures and application mappings. The mainstream evaluation technique today is the system-level performance simulation of the applications and platforms using abstracted workload and processing capacity models, respectively. These virtual system models allow fast simulation of large systems at an early phase of development with reasonable modeling effort and time. The accuracy of the performance results is dependent on how closely the models used reflect the actual system. This paper presents a compiler based technique for automatic generation of workload models for performance simulation, while exploiting an overall approach and platform performance capacity models developed previously. The resulting workload models are experimented using x264 video and JPEG encoding application examples.
  • Keywords
    embedded systems; program compilers; application mapping; automatic generation; automatic workload generation; compiler based technique; design space; embedded system; modified GCC compiler; system level exploration; system-level performance simulation; virtual system model; Abstracts; Application software; Computational modeling; Computer architecture; Delay; Embedded system; Encoding; Mobile computing; Performance evaluation; Processor scheduling;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design, Automation & Test in Europe Conference & Exhibition (DATE), 2010
  • Conference_Location
    Dresden
  • ISSN
    1530-1591
  • Print_ISBN
    978-1-4244-7054-9
  • Type

    conf

  • DOI
    10.1109/DATE.2010.5457175
  • Filename
    5457175