Title :
Measurement results of substrate bias dependency on Negative Bias Temperature Instability degradation in a 65 nm process
Author :
Tanihiro, S. ; Yabuuchi, M. ; Kobayashi, Kaoru
Author_Institution :
Dept. of Electron., Kyoto Inst. of Technol., Matsugasaki, Japan
Abstract :
The transistor size keeps shrinking by Moore´s law and timing degradation of the scaled transistors is becoming critical. Recently, the scaling of CMOS technology increases the effect of NBTI (Negative Bias Temperature Instability) in PMOS. NBTI is an important reliability issue for analog as well as digital CMOS circuits. As transistors are scaled refined, the impact of NBTI becomes more critical. This paper deals with relationship between NBTI and the substrate bias. If the substrate bias go a forward, degradation of NBTI is accelerated. We show measurement results of degradation due to NBTI according to the forward and reverse body biases.
Keywords :
CMOS integrated circuits; integrated circuit reliability; negative bias temperature instability; Moore law; PMOS; digital CMOS circuits; negative bias temperature instability degradation; size 65 nm; substrate bias dependency; timing degradation; transistor size;
Conference_Titel :
CPMT Symposium Japan, 2012 2nd IEEE
Conference_Location :
Kyoto
Print_ISBN :
978-1-4673-2654-4
DOI :
10.1109/ICSJ.2012.6523441