A Fast Test Architecture for Asynchronous Network-on-Chip Routing Networks

Author

Baek, Chul-Ki ; Kim, Insoo ; Kim, Jung-Tae ; Kim, Yong-Hyun ; Min, Hyoung Bok ; Lee, Jae-Hoon

Author_Institution

Sch. of Inf. & Commun. Eng., Sungkyunkwan Univ., Suwon, South Korea

fYear

2010

fDate

11-13 Aug. 2010

Firstpage

1

Lastpage

4

Abstract

ANoC (Asynchronous Network-on-Chip) has been developed to solve problems of large number of cores in SoC (System-on-Chip) by giving asynchronism to every core. This new architecture requires new Testing methods different from the existing SoC Test, and it freshly needs the test of router and routing networks. This paper first offers high-speed testing architecture that tests more than one routers and networks at the same time in the 2-D mesh topology. Then, the structure of wrapper for realization of this method is explained. We show that the more number of routers is, the more effective performance is by checking the clock count for test of various ANoCs that have several sizes.

Keywords

asynchronous circuits; clocks; design for testability; microprocessor chips; multiprocessing systems; network routing; network-on-chip; 2D mesh topology; SoC test; asynchronous network-on-chip routing network; clock count; fast test architecture; high speed testing architecture; testing method; Clocks; Computer architecture; Memory; Microprocessors; Routing; System-on-a-chip; Testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Information Technology Convergence and Services (ITCS), 2010 2nd International Conference on

Conference_Location

Cebu

Print_ISBN

978-1-4244-7584-1

Electronic_ISBN

978-1-4244-7584-1

Type

conf

DOI

10.1109/ITCS.2010.5581281

Filename

5581281