• DocumentCode
    2258887
  • Title

    Placement-aware 3D floorplanning

  • Author

    Nain, Rajeev K. ; Chrzanowska-Jeske, Malgorzata

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Portland State Univ., Portland, OR, USA
  • fYear
    2009
  • fDate
    24-27 May 2009
  • Firstpage
    1727
  • Lastpage
    1730
  • Abstract
    We present a novel 3D floorplanning algorithm with module splitting (3D-FMS). The proposed methodology allows designers to introduce and evaluate an assignment of vertically-aligned parts of the same module to different device layers. Our experimental results on MCNC and GSRC benchmarks show that 3D-FMS can generate a good floorplanning solution with reduced wirelength inside modules and optimized footprint area while controlling the number of vias. Compared to the existing state-of-the-art 3D floorplanning algorithms, 3D-FMS reduces the system level total wirelength by 7.9%.
  • Keywords
    circuit layout CAD; integrated circuit layout; floorplanning solution; footprint area; module splitting; placement-aware 3D floorplanning; three dimensional integrated circuits; Design automation; Design methodology; Integrated circuit interconnections; Integrated circuit technology; Microprocessors; Partitioning algorithms; Simulated annealing; Thermal resistance; Very large scale integration; Wires;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems, 2009. ISCAS 2009. IEEE International Symposium on
  • Conference_Location
    Taipei
  • Print_ISBN
    978-1-4244-3827-3
  • Electronic_ISBN
    978-1-4244-3828-0
  • Type

    conf

  • DOI
    10.1109/ISCAS.2009.5118108
  • Filename
    5118108