DocumentCode
2258909
Title
Representation of 3D-LSI floorplan based on stacked-rectangular-dissection
Author
Ohta, Hidenori ; Fujiyoshi, Kunihiro
Author_Institution
Dept. of Electr. & Inf. Eng., Tokyo Univ. of Agric. & Technol., Tokyo, Japan
fYear
2009
fDate
24-27 May 2009
Firstpage
1731
Lastpage
1734
Abstract
Recently, 3D-LSIs which consist of several silicon layers have been developed and have attracted attention. 3D-LSI has an advantage of the length of wires and the number of components per chip. However, a layout design of the 3D-LSIs will be much complex. In this paper, we propose a stacked-rectangular-dissection, which consists of several rectangular dissections, as a floorplan of 3D-LSI. And to search for a good floorplan of 3D-LSI with simulated annealing, a representation of a stacked-rectangular-dissection is presented.
Keywords
integrated circuit layout; large scale integration; simulated annealing; 3D-LSI floorplan representation; rectangular dissections; silicon layers; simulated annealing; stacked-rectangular-dissection; Agricultural engineering; Agriculture; Large scale integration; Silicon; Simulated annealing; Sufficient conditions; Wires; Wiring;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2009. ISCAS 2009. IEEE International Symposium on
Conference_Location
Taipei
Print_ISBN
978-1-4244-3827-3
Electronic_ISBN
978-1-4244-3828-0
Type
conf
DOI
10.1109/ISCAS.2009.5118109
Filename
5118109
Link To Document