AVGS-Mux style: A novel technology and device independent technique for reducing power and compensating process variations in FPGA fabrics

Author

Kheradmand-Boroujeni, Bahman ; Piguet, Christian ; Leblebici, Yusuf

Author_Institution

Integrated & Wireless Syst., CSEM, Neuchatel, Switzerland

fYear

2010

fDate

8-12 March 2010

Firstpage

339

Lastpage

344

Abstract

This work presents Adaptive Vgs Multiplexer (AVGS-Mux) Technique. Proposed method controls the transistor current by the source voltage. It can provide ??1.6X control on the delay and ??7X exponential control on sub-threshold and gate leakages in the switch-box, LUT, and interconnects. For equal leakage, it improves the speed 9%, reduces dynamic power 13%, and reduces random dopant fluctuations effect. AVGS-Mux is a good replacement of adaptive body biasing and adaptive supply voltage techniques in emerging Multi-Gate devices which have very small body effect and cannot tolerate voltages higher than nominal VDD due to reliability issues.

Keywords

field programmable gate arrays; integrated circuit interconnections; FPGA fabrics; LUT; adaptive Vgs multiplexer technique; adaptive body biasing; adaptive supply voltage technique; exponential control; gate leakages; multigate devices; power reduction; process variation compensation; switch-box; transistor current control; Delay; Fabrics; Field programmable gate arrays; Flip-flops; Logic; Multiplexing; Page description languages; Switches; Table lookup; Voltage; FPGA fabric; adaptive supply voltage; body biasing; inter-die process variation; leakage; low-power; source biasing;

fLanguage

English

Publisher

ieee

Conference_Titel

Design, Automation & Test in Europe Conference & Exhibition (DATE), 2010

Conference_Location

Dresden

ISSN

1530-1591

Print_ISBN

978-1-4244-7054-9

Type

conf

DOI

10.1109/DATE.2010.5457182

Filename

5457182