Title :
VLSI Implementation of a 4×4 MIMO-OFDM transceiver with an 80-MHz channel bandwidth
Author :
Yoshizawa, Shingo ; Miyanaga, Yoshikazu
Author_Institution :
Grad. Sch. of Inf. Sci. & Technol., Hokkaido Univ., Sapporo, Japan
Abstract :
VLSI implementation for a 4times4 multiple-input multiple-output orthogonal frequency division multiplexing (MIMO-OFDM) transceiver is described that targets 1-Gbps data transmission for next-generation wireless LAN systems. The IEEE802.11 Very High Throughput (VHT) Study Group concluded that a signal bandwidth of more than 80 MHz is needed to achieve 1-Gbps throughput in the MAC layer. The proposed architecture is suitable for VLSI implementation that meets this specification and enables real-time processing in a 4times4 MIMO-OFDM configuration. It incorporates a minimum mean-square error (MMSE) MIMO detector that drastically shortens processing latency. Evaluation of a MIMO-OFDM transceiver implemented in CMOS with 128, 256, or 512 OFDM subcarriers showed that the power dissipation ranged from 451 to 577 mW.
Keywords :
MIMO communication; OFDM modulation; VLSI; access protocols; transceivers; wireless LAN; wireless channels; 4times4 MIMO-OFDM transceiver; IEEE802.11; MAC layer; VLSI implementation; channel bandwidth; frequency 80 MHz; minimum mean-square error MIMO detector; multiple-input multiple-output systems; power 451 mW to 577 mW; power dissipation; real-time processing; wireless LAN systems; Bandwidth; Data communication; Delay; Detectors; MIMO; OFDM; Throughput; Transceivers; Very large scale integration; Wireless LAN;
Conference_Titel :
Circuits and Systems, 2009. ISCAS 2009. IEEE International Symposium on
Conference_Location :
Taipei
Print_ISBN :
978-1-4244-3827-3
Electronic_ISBN :
978-1-4244-3828-0
DOI :
10.1109/ISCAS.2009.5118112
