DocumentCode :
2259006
Title :
Low complexity hardware interleaver for MIMO-OFDM based wireless LAN
Author :
Asghar, Rizwan ; Liu, Dake
Author_Institution :
Dept. of Electr. Eng., Linkoping Univ., Linkoping, Sweden
fYear :
2009
fDate :
24-27 May 2009
Firstpage :
1747
Lastpage :
1750
Abstract :
A low complexity hardware interleaver architecture is presented for MIMO-OFDM based wireless LAN e.g. 802.11n. Novelty of the presented architecture is twofold; 1) Flexibility to choose interleaver implementation with different modulation scheme and different size for different spatial streams in a multi antenna system, 2) Complexity to compute on the fly interleaver address is reduce by using recursion and is supported by mathematical formulation. The proposed interleaver architecture is implemented on 65 nm CMOS process and it consumes 0.035 mm2 area. The proposed architecture supports high speed communication with maximum throughput of 900 Mbps at a clock rate of 225 MHz.
Keywords :
CMOS integrated circuits; MIMO communication; OFDM modulation; communication complexity; wireless LAN; CMOS process; MIMO-OFDM; bit rate 900 Mbit/s; clock rate; frequency 225 MHz; high speed communication; low complexity hardware interleaver architecture; modulation scheme; multiantenna system; size 65 nm; wireless LAN; CMOS process; Clocks; Computer architecture; Equations; Hardware; Interleaved codes; Radio frequency; Throughput; WiMAX; Wireless LAN;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems, 2009. ISCAS 2009. IEEE International Symposium on
Conference_Location :
Taipei
Print_ISBN :
978-1-4244-3827-3
Electronic_ISBN :
978-1-4244-3828-0
Type :
conf
DOI :
10.1109/ISCAS.2009.5118113
Filename :
5118113
Link To Document :
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