Title :
Chip-based hetero-integration technology for high-performance 3D stacked image sensor
Author :
Ohara, Yuki ; Kang Wook Lee ; Kiyoyama, K. ; Konno, Shuji ; Sato, Yuuki ; Watanabe, Shigetaka ; Yabata, A. ; Kobayashi, Hideo ; Kamada, Tomonari ; Bea, Jichel ; Murugesan, Mariappan ; Hashimoto, Hiroya ; Fukushima, Tetsuya ; Tanaka, T. ; Koyanagi, Mitsuma
Author_Institution :
Tohoku Univ., Sendai, Japan
Abstract :
We have developed a 3D-stacked image sensor chip composed of CMOS image sensor (CIS) layer, correlated double sampling circuit (CDS) layer, and analog-to-digital converter (ADC) array layer using the chip-based 3D heterogeneous integration technology. Three kinds of chips, CIS chip, CDS chip, and ADC chip, which were fabricated by different technologies, are processed and stacked vertically to form a prototype 3D-stacked image sensor. Through-Si vias (TSVs) and metal micro-bumps are formed in chip-level before stacking. The fundamental characteristics are evaluated in the fabricated prototype 3D-stacked image sensor.
Keywords :
CMOS image sensors; integrated circuit manufacture; three-dimensional integrated circuits; 3D-stacked image sensor chip; ADC chip; CDS chip; CIS chip; CMOS image sensor layer; analog-to-digital converter array layer; chip-based 3D heterogeneous integration technology; chip-based hetero-integration technology; correlated double sampling circuit layer; metal micro-bumps; through-silicon-via;
Conference_Titel :
CPMT Symposium Japan, 2012 2nd IEEE
Conference_Location :
Kyoto
Print_ISBN :
978-1-4673-2654-4
DOI :
10.1109/ICSJ.2012.6523452
