Finfet with isolated n+ and p+ gate regions strapped with metal and polysilicon

A vertical double gate MOSFET structure with a new gate stack architecture has been demonstrated. The gate stack consists of two isolated polysilicon regions that are doped N+ and P+ with a metal/polysilicon strap connecting the doped regions. The device has an undoped channel yet performs as an enhancement mode MOSFET due to the asymetric doping of the gate regions on either side of the channel. The advantages of this structure include: 1) reduction of the Vt variations caused by dopant fluctuation in the channel region; 2) enhanced mobility due to an undoped channel region; 3) flexibility to adjust Vt across a wide range from depletion mode to very high Vt depending on the application; 4) lower interconnect resistance due to the use of metal/polysilicon gate components; 5) better manufacturability due to easier patterning of gate over spacer. The devices are enhancement mode with Vt ∼=(0.1-0.3V) at 100 nm gate length and channel thickness of less than 30 nm gate length and height 100 nm tall have been demonstrated. Functional devices at the 100 nm gate have Ion=191 μA/μm, Vt=0.3 V Ioff =0.5 μA/μm, SS=94 mV/decade. A different device with different implant dose and drive demonstrated Vt=0.15 V and SS=80mV/decade at Lgate=0.25 μm.