• DocumentCode
    2259051
  • Title

    Heterogeneous 3D Stacking technology developments in ASET

  • Author

    Ikeda, Hinata

  • Author_Institution
    Assoc. of Super-Adv. Electron. Technol. (ASET), Tokyo, Japan
  • fYear
    2012
  • fDate
    10-12 Dec. 2012
  • Firstpage
    1
  • Lastpage
    4
  • Abstract
    For TSV/3D-Stacking technology developments, Memory Cubes (such as 4-high stack DDR3 SDRAM, Wide-IO DRAM and HMC) have been leading the progress of the technologies [1], [2].
  • Keywords
    DRAM chips; three-dimensional integrated circuits; ASET; DDR3 SDRAM; TSV; heterogeneous 3D stacking technology development; memory cubes; wide IO DRAM;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    CPMT Symposium Japan, 2012 2nd IEEE
  • Conference_Location
    Kyoto
  • Print_ISBN
    978-1-4673-2654-4
  • Type

    conf

  • DOI
    10.1109/ICSJ.2012.6523453
  • Filename
    6523453
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2259051