Spacer FinFET: nano-scale CMOS technology for the terabit era

Author

Choi, Yang-Kyu ; King, Tsu-Jae ; Hu, Chenming

Author_Institution

Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA

fYear

2001

fDate

2001

Firstpage

543

Lastpage

546

Abstract

A spacer lithography process technology using a sacrificial layer and a CVD (Chemical Vapor Deposition) spacer layer has been developed, and is demonstrated to achieve sub-40 nm structures with conventional dry etching. The minimum-sized features are defined not by photolithography but by the CVD film thickness. Therefore the spacer lithography technology yields CD (Critical Dimension) variations of minimum-sized features which are much smaller than achieved by optical or e-beam lithography. It also provides a doubling of device density for a given lithography pitch. This spacer lithography technology is used to pattern Si-fin structures for double-gate MOSFETs (FinFETs), and CMOS FinFET results are reported

Keywords

CMOS integrated circuits; MOSFET; chemical vapour deposition; nanotechnology; oxidation; photolithography; silicon-on-insulator; sputter etching; 6.5 nm; 60 nm; CD variations; CMOS FinFET; CVD film thickness; CVD spacer layer; Si-fin structure patterning; Si_0.4Ge_0.6; device density doubling; double-gate MOSFETs; dry etching; i-line optical lithography; lithography pitch; minimum-sized features; nano-scale CMOS technology; sacrificial layer; short-channel behavior; spacer FinFET; spacer lithography process technology; sub-40 nm structures; thermal oxidation; thin-body SOI devices; CMOS technology; Chemical technology; Fabrication; FinFETs; Leakage current; Lithography; Optical films; Space technology; Thermal stresses; Throughput;

fLanguage

English

Publisher

ieee

Conference_Titel

Semiconductor Device Research Symposium, 2001 International

Conference_Location

Washington, DC

Print_ISBN

0-7803-7432-0

Type

conf

DOI

10.1109/ISDRS.2001.984573

Filename

984573