Title :
Reducing indirect programming mismatch due to oxide-traps using dual-channel floating-gate transistors
Author :
Huang, Chenling ; Chakrabartty, Shantanu
Author_Institution :
Dept. of Electr. & Comput. Eng., Michigan State Univ., East Lansing, MI, USA
Abstract :
This paper presents a dual-channel architecture for floating-gate transistors that can alleviate the detrimental effects of oxide-traps seen in indirect programming techniques. The proposed transistor consists of four input/output ports that allow multiple paths for drain currents to flow and yet share the same gate-oxide and poly-silicon gate. As a result, one pair of the ports can be used for indirect programming, whereas the other pair can be actively connected to other analog circuits. Compared with the existing approaches for floating-gate programming, the proposed technique avoids disruption of the circuit operation and eliminates the effect of oxide-traps as well. In this paper we present measured results obtained from a dual-channel floating-gate current reference which has been fabricated in a 0.5-mum standard CMOS process.
Keywords :
CMOS integrated circuits; floating point arithmetic; mathematical programming; CMOS process; analog circuits; dual-channel architecture; dual-channel floating-gate transistors; gate-oxide; indirect programming mismatch; oxide-traps; poly-silicon gate; size 0.5 mum; Analog circuits; Current measurement; MOSFETs; Measurement standards; Mirrors; Nonvolatile memory; Secondary generated hot electron injection; Switches; Threshold voltage; Tunneling;
Conference_Titel :
Circuits and Systems, 2009. ISCAS 2009. IEEE International Symposium on
Conference_Location :
Taipei
Print_ISBN :
978-1-4244-3827-3
Electronic_ISBN :
978-1-4244-3828-0
DOI :
10.1109/ISCAS.2009.5118122