DocumentCode
2259195
Title
PDN characteristics of 3D-SiP with a wide-bus structure under 4k-IO operations
Author
Sakai, Akihiko ; Yamada, Shigeru ; Kariya, Tsuyoshi ; Uchiyama, S. ; Ikeda, Hinata ; Fujita, Hideaki ; Takatani, Hiroki ; Tanaka, Yuichi ; Oizono, Y. ; Nabeshima, Yuji ; Sudo, Toshio
Author_Institution
Assoc. of Super-Adv. Electron. Technol. (ASET), Tokyo, Japan
fYear
2012
fDate
10-12 Dec. 2012
Firstpage
1
Lastpage
4
Abstract
The 4096 bits wide-bus three-dimensional integration device using through-silicon-vias (TSVs) has been designed and fabricated as a demonstrator for power integrity such as power distribution network (PDN) impedance and simultaneous switching output (SSO) noise characteristics. Anti-resonance peak of total PDN impedance was extracted at around 80 MHz. This result was well coincident with maximum SSO noise frequency at around 75 MHz. Further, SSO noise reduction clocking named phase-shift clock has also been implemented to demonstrate the effectiveness as measurement basis.
Keywords
clocks; integrated circuit design; integrated circuit interconnections; integrated circuit noise; system-in-package; three-dimensional integrated circuits; word length 4096 bit;
fLanguage
English
Publisher
ieee
Conference_Titel
CPMT Symposium Japan, 2012 2nd IEEE
Conference_Location
Kyoto
Print_ISBN
978-1-4673-2654-4
Type
conf
DOI
10.1109/ICSJ.2012.6523460
Filename
6523460
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