Title :
Towards a chip level reliability simulator for copper/low-k backend processes
Author :
Bashir, Muhammad ; Milor, Linda
Author_Institution :
Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA
Abstract :
A framework is proposed to analyze circuit layout geometries to predict chip lifetime due to low-k time-dependent dielectric breakdown (TDDB). The methodology uses as inputs data from test structures, which have been designed and fabricated to detect the impact of area and metal linewidth on low-k TDDB.
Keywords :
copper; electric breakdown; integrated circuit layout; integrated circuit manufacture; integrated circuit reliability; Cu; chip level reliability simulator; chip lifetime; circuit layout geometries; copper/low-k backend processes; low-k time-dependent dielectric breakdown; Analytical models; Computational modeling; Copper; Dielectric breakdown; Dielectric materials; Electric breakdown; Integrated circuit interconnections; Power system interconnection; Predictive models; Temperature;
Conference_Titel :
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2010
Conference_Location :
Dresden
Print_ISBN :
978-1-4244-7054-9
DOI :
10.1109/DATE.2010.5457195
