An Extended Phase Detector 2.56/3.2Gb/s Clock And Data Recovery design with Digitally Assisted Lock Detector

In the paper, a novel 2.56/3.2Gb/s full-rate phase detector is developed for integration with clock data recovery (CDR) circuit in high speed SerDes applications. An extended phase detector (EPD) circuit is proposed to replace the full-rate Hogge architecture. To incorporate a LC-tank voltage control oscillator with cross-coupled pair and a differential charge pump with common mode feedback. The digitally assisted lock detector (DALD) circuitry provides a timing decision for switching dual loops between phase or frequency detector in the 6MR circuits. The CDR circuit is fabricated in a 0.18 mum 1P6M standard CMOS process in an area of 0.8times1.0 mm². This CDR chip exhibits a low jitter performance of 2.12 ps RMS in the recovered clock and a BER is 3.5 times 10-9 with PRBS of 231-1 sequence. The power consumption is 136 mW with a 1.8 V supply at 3.2 Gb/s.