Title :
10Gbps decision feedback equalizer with dynamic lookahead decision loop
Author :
Lin, Yu-Chun ; Shiue, Muh-Tian ; Jou, Shyh-Jye
Author_Institution :
Dept. of Electr. Eng., Nat. Central Univ., Taoyuan, Taiwan
Abstract :
Decision feedback equalizer (DFE) uses a feedback path to cancel post-cursor ISI, and this feedback path will also cause the limitation of its maximum throughput rate. This paper proposes a new lookahead method to break the feedback path for multi-gigabit DFE design. After lookahead computation, each paralleled sub-circuit has the same throughput rate as original one. Therefore, the total throughput rate is proportional to the parallelization factor. The computation complexity of the proposed architecture is lower than that of multiplexer-based lookahead DFE if the tap number of the feedback filter is large. It is shown that the new method saves 10% hardware complexity for an 8 taps feedback filter DFE and 98% hardware complexity for a 12 taps feedback filter DFE in comparison to a 10 Gbps multiplexer-based lookahead DFE.
Keywords :
decision feedback equalisers; filtering theory; interference suppression; intersymbol interference; multiplexing equipment; bit rate 10 Gbit/s; decision feedback equalizer; dynamic lookahead decision loop; feedback filter DFE comparison; feedback path; multigigabit DFE design; multiplexer-based lookahead DFE; paralleled subcircuit; parallelization factor; post-cursor ISI cancellation; Adders; Control systems; Decision feedback equalizers; Feedback loop; Field-flow fractionation; Finite impulse response filter; Hardware; Multiplexing; Niobium; Throughput;
Conference_Titel :
Circuits and Systems, 2009. ISCAS 2009. IEEE International Symposium on
Conference_Location :
Taipei
Print_ISBN :
978-1-4244-3827-3
Electronic_ISBN :
978-1-4244-3828-0
DOI :
10.1109/ISCAS.2009.5118136