Title :
Comparison of on-die global clock distribution methods for parallel serial links
Author :
Hu, Kangmin ; Jiang, Tao ; Chiang, Patrick
Author_Institution :
OSU VLSI Res. Group, Oregon State Univ., Corvallis, OR, USA
Abstract :
This paper presents a comparative study of clock distribution methods for serial links, including inverter chain, CML chain, transmission line, inductive load and capacitively driven wires in regards to delay, jitter and power consumption. Analysis, simulation and design insights are given for each method for 2.5 GHz clock propagation by on-die 5 mm wire in a 90 nm CMOS process. Simulations show the transmission line achieves least jitter and delay, while capacitively driven wire illustrates the best power-jitter and power-delay product.
Keywords :
CMOS integrated circuits; clocks; integrated circuit design; CML chain; CMOS; capacitively driven wires; clock propagation; frequency 2.5 GHz; inductive load; inverter chain; on-die global clock distribution methods; parallel serial links; power consumption; power-delay product; power-jitter; size 5 mm; size 90 nm; transmission line; CMOS process; Capacitance; Circuits; Clocks; Energy consumption; Inverters; Jitter; Power transmission lines; Propagation delay; Wire; Clock distribution; jitter; serial link;
Conference_Titel :
Circuits and Systems, 2009. ISCAS 2009. IEEE International Symposium on
Conference_Location :
Taipei
Print_ISBN :
978-1-4244-3827-3
Electronic_ISBN :
978-1-4244-3828-0
DOI :
10.1109/ISCAS.2009.5118137
