Title :
The role of dynamic threshold shifts in the performance of inverters and NAND gates in PD SOI technology
Author :
Ketchen, Mark B.
Author_Institution :
IBM Res., Yorktown Heights, NY, USA
fDate :
29 Sept.-2 Oct. 2003
Abstract :
In this paper, a method is described for quantifying DTS effects in PD SOI. If one chooses to characterize SOI with a single nFET Vt (and single pFET Vt) of the "equivalent" bulk technology, the additional drive enhancement due to DTS amounts at most to a few % for the 0.18 μm technology case considered. Buried within this characterization are much larger DTS effects that can be studied within the same framework. The results suggest there is opportunity for further DTS advantage for PD SOI by decreasing the drain-body capacitance compared to the gate-body capacitance.
Keywords :
capacitance; elemental semiconductors; field effect transistors; logic gates; semiconductor device models; silicon-on-insulator; threshold logic; 0.18 micron; NAND gates; Si; drain-body capacitance; dynamic threshold shifts; inverters; nFET; partially depleted SOI technology; Capacitance; FETs; Semiconductor device modeling; Silicon on insulator technology; Threshold logic;
Conference_Titel :
SOI Conference, 2003. IEEE International
Print_ISBN :
0-7803-7815-6
DOI :
10.1109/SOI.2003.1242941
