Title :
Low voltage/low power sub 50 nm double gate SOI ratioed logic
Author :
Mitra, Souvick ; Salman, Akram ; Ioannou, Dimitris P. ; Tretz, Christophe ; Ioannou, Dimitris E.
Author_Institution :
Dept. of Electr. & Comput. Eng., George Mason Univ., Fairfax, VA, USA
fDate :
29 Sept.-2 Oct. 2003
Abstract :
In this paper, we show how the approach can also be used to built NAND and XOR gates to create a complete logic family. This is the first report that proposes a unique building block for a comprehensive DG-SOI logic design style along with a gain in number of devices used without compromising the performance superiority. All simulations are done for 50 nm gate length devices using SILVACO tools.
Keywords :
elemental semiconductors; logic design; logic gates; logic simulation; silicon-on-insulator; 50 nm; Low voltage/low power sub 50 nm double gate SOI ratioed logic; NAND gates; Si; XOR gates; dual gate-SOI logic design; gate length devices; logic simulation; Logic design; Silicon on insulator technology;
Conference_Titel :
SOI Conference, 2003. IEEE International
Print_ISBN :
0-7803-7815-6
DOI :
10.1109/SOI.2003.1242942
