Pulse mode multilayer neural network with floating point operation and on-chip learning

Describes a pulse mode hardware multilayer neural network (MNN) that uses a floating point number system for synapse weights. Combined with pulse mode operation, the floating point operation is implemented without multipliers. Furthermore, the backpropagation algorithm is included in the hardware to provide on-chip learning capability. The proposed MNN is implemented on a field programmable gate array (FPGA) and various experiments are conducted to test the performance of the proposed system. The results of the experiments show that the proposed MNN architecture can be used for applications that require high precision in their calculation, and its good on-chip learning capability is also demonstrated