FPGA implementation of hardware countermeasures

Author

Jimenez, R. ; Feria, G. ; Sdnchez-Raya, M. ; Galan, J. ; Gomez, F.

Author_Institution

Dipt. Ing. Electron. de Sist. Informaticos y Autom., Univ. de Huelva, Huelva, Spain

fYear

2012

fDate

20-23 March 2012

Firstpage

1

Lastpage

6

Abstract

A FPGA implementation of a frequency sensor has been presented. Its main mission consists to determine when the frequency of test signal is into an allowed range. This implementation has the following configurable parameters: timing resolution and allowed range of frequency. This component operates in real-time with a delay of only one operation cycle. Countermeasures against clock glitch attacks is one of its possible applications. Experimental results in a Spartan-3AN700 device show a minimum allowed period of about 16 ns and a minimum resolution of about 4 ns. The implementation of the sensor has been verified in an electronic lock, used as a case of study. This system has been attacked with clock glitches, showing its behavior without and with sensor.

Keywords

cryptography; embedded systems; field programmable gate arrays; frequency control; sensors; FPGA implementation; Spartan-3AN700 device; clock glitch; clock glitch attack; configurable parameter; electronic lock; frequency sensor; hardware countermeasure; test signal; timing resolution;

fLanguage

English

Publisher

ieee

Conference_Titel

Programmable Logic (SPL), 2012 VIII Southern Conference on

Conference_Location

Bento Goncalves

Print_ISBN

978-1-4673-0184-8

Type

conf

DOI

10.1109/SPL.2012.6211766

Filename

6211766