FPGA implementation of robust asynchronous wrappers for Globally-Asynchronous systems (GALS)

Contemporary digital systems must be based on the “System-on-Chip - SoC” concept. An interesting style for SoC design is the GALS paradigm (Globally Asynchronous, Locally Synchronous), which can be used to implement circuits in FPGAs (Field Programmable Gate Arrays), but the implementation of asynchronous interfaces (asynchronous wrapper - AW) constitutes a major drawback for this kind of devices. Although there is a typical AW design style which is based on asynchronous controllers and provides communication between modules (called ports), Port controllers are subject to essential-hazard when implemented FPGA. In this context, this paper proposes a new asynchronous GALS wrapper architecture to be implemented in FPGAs that is essentially free from hazard, not needing any special cares in implementation concerning to LUTs choice and being fully compatible with FPGA. Additional advantages of the proposed architecture are the total autonomy that synchronous modules achieve when interacting with the asynchronous wrapper; its ports can be synthesized in the direct mapping style (so without knowledge of asynchronous logic synthesis); and ports interacts in Ib/Ob Mode, not needing a timing analysis and also being more robust than GFM.