Title :
Real-time scheduling coprocessor for NIOS II processor
Author :
Varela, M. ; Cayssials, R. ; Ferro, E. ; Boemo, E.
Author_Institution :
Dept. of Electr. Eng., Univ. Nac. del Sur, Bahia Blanca, Argentina
Abstract :
In this paper we describe and analyze the main features of the Hardware Real-Time Scheduler Coprocessor unit (HRTC) for NIOS II processor. We describe how the HRTSC supports time, events, task and priorities. The HRTSC was designed as a SOPC component to incorporate real-time features for embedded real-time applications. The hardware architecture has an easy integration with the IDE programming environment. The Avalon interface showed to be an efficient specification to share memory and data communication among memory, processor and HRTSC. The performance of the HRTSC architecture is analyzed considering real-time flexibility, programmability and power consumption reduction.
Keywords :
coprocessors; embedded systems; processor scheduling; real-time systems; Avalon interface; HRTSC architecture; IDE programming environment; NIOS II processor; SOPC component; data communication; embedded real-time application; hardware architecture; hardware real-time scheduler coprocessor unit; power consumption reduction; real-time flexibility; real-time programmability; real-time scheduling coprocessor; Hardware; Memory management; Processor scheduling; Random access memory; Real time systems; Registers; Scheduling; NIOS II Processor; Real-Time; SOPC Component;
Conference_Titel :
Programmable Logic (SPL), 2012 VIII Southern Conference on
Conference_Location :
Bento Goncalves
Print_ISBN :
978-1-4673-0184-8
DOI :
10.1109/SPL.2012.6211775
