Title :
Generic construction of monitors for Floating Point Unit designs
Author :
Goñi, Oscar ; Todorovich, Elías ; Cadenas, Oswaldo
Author_Institution :
INTIA Inst., Univ. Nac. del Centro de la Provincia de Buenos Aires, Buenos Aires, Argentina
Abstract :
This paper proposes a set of well defined steps to design functional verification monitors intended to verify Floating Point Units (FPU) described in HDL. The first step consists on defining the input and output domain coverage. Next, the corner cases are defined. Finally, an already verified reference model is used in order to test the correctness of the Device Under Verification (DUV). As a case study a monitor for an IEEE754-2008 compliant design is implemented. This monitor is built to be easily instantiated into verification frameworks such as OVM. Two different designs were verified reaching complete input coverage and successful compliant results.
Keywords :
floating point arithmetic; integrated circuit testing; microprocessor chips; HDL; IEEE754-2008 compliant design; design functional verification monitor; device under verification; floating point unit design; monitor generic construction; verification framework; Adders; Encoding; Generators; Hardware design languages; Modeling; Monitoring; Standards;
Conference_Titel :
Programmable Logic (SPL), 2012 VIII Southern Conference on
Conference_Location :
Bento Goncalves
Print_ISBN :
978-1-4673-0184-8
DOI :
10.1109/SPL.2012.6211776
