• DocumentCode
    2260451
  • Title

    Enabling GPU and Many-Core Systems in Heterogeneous HPC Environments Using Memory Considerations

  • Author

    Guim, Francesc ; Rodero, Ivan ; Corbalan, Julita ; Parashar, Manish

  • Author_Institution
    Comput. Archit. Dept., Tech. Univ. of Catalonia (UPC), Barcelona, Spain
  • fYear
    2010
  • fDate
    1-3 Sept. 2010
  • Firstpage
    146
  • Lastpage
    155
  • Abstract
    Increasing the utilization of many-core systems has been one of the forefront topics these last years. Although many-cores architectures were merely theoretical models few years ago, they have become an important part of the high performance computing market. The semiconductor industry has developed Graphical Processing Units (GPU) systems that provide access to many cores (i.e: Larrabee, Fermi or Tesla) that can be used for General Purpose (GP) computing. In this paper, we propose and evaluate a scheduling strategy for GPU and many-core architectures for HPC environments. Specifically, our strategy is a variant of the backfilling scheduling policy with resource sharing considerations. We propose a scheduling strategy that considers the differences between GP processors and GPU computing elements in terms of computational capacity and memory bandwidth. To do this, our approach uses a resource model that predicts how shared resources are used in both GP and GPU/many-core elements. Furthermore, it considers the differences between these elements in terms of performance. First, it models their differences in terms of computational power and how they share the access to the node´s memory bandwidth. Second, it characterizes how the processes are allocated to the GPU. Using this resource model, we design the Power Aware resource selection policy, which we combine with the LessConsume scheduling policy. Our strategy tries to allocate jobs aiming at reducing the memory contention and the energy consumption. Results show that the scheduling strategies proposed in this work are able to save over 40% of energy and improve the system performance up to 30% with respect to traditional backfilling strategies.
  • Keywords
    computer graphic equipment; coprocessors; multiprocessing systems; power aware computing; scheduling; backfilling scheduling policy; general purpose computing; graphical processing units; heterogeneous HPC environments; high performance computing market; many core architectures; many core systems; memory considerations; power aware resource selection policy; resource sharing; semiconductor industry; DVS; GPU; Job Scheduling; memory considerations;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    High Performance Computing and Communications (HPCC), 2010 12th IEEE International Conference on
  • Conference_Location
    Melbourne, VIC
  • Print_ISBN
    978-1-4244-8335-8
  • Electronic_ISBN
    978-0-7695-4214-0
  • Type

    conf

  • DOI
    10.1109/HPCC.2010.29
  • Filename
    5581357