Title :
VLSI circuits for optoelectronic neural network weight setting
Author :
Chew, Chwei-po ; Newcomb, Roben W. ; Yuh, Jen-Dong
Author_Institution :
Dept. of Electr. Eng., Maryland Univ., College Park, MD, USA
Abstract :
A VLSI optoelectronic implementation of matrix multiplication, which is useful for image-processing applications using neural networks, is presented. BiCMOS NPN and PNP phototransistors generate excitatory and inhibitory synapse currents when light shines on them. These synapse currents are controlled by complementary MOS transistors which allow us to program real valued weights. Differential amplifiers are used to sum the synapse currents while transmission gates are used as resistors. We present an example for digital weight interconnections with 5 bits resolution plus a sign. Circuit diagrams, SPICE3el circuit simulations, a NPN phototransistor magic layout, and a phototransistor measurement are also given
Keywords :
BiCMOS integrated circuits; VLSI; differential amplifiers; matrix multiplication; neural net architecture; optical neural nets; phototransistors; BiCMOS; NPN phototransistors; PNP phototransistors; SPICE3el circuit simulations; VLSI circuits; complementary MOS transistors; differential amplifiers; digital weight interconnections; excitatory currents; image-processing; inhibitory synapse currents; matrix multiplication; optoelectronic neural network; phototransistor measurement; real valued weights; transmission gates; weight setting; Adaptive filters; BiCMOS integrated circuits; CMOS technology; Integrated circuit interconnections; MOSFETs; Neural networks; Neurons; Phototransistors; Resistors; Very large scale integration;
Conference_Titel :
Circuits and Systems, 1993., Proceedings of the 36th Midwest Symposium on
Conference_Location :
Detroit, MI
Print_ISBN :
0-7803-1760-2
DOI :
10.1109/MWSCAS.1993.342938
