A programmable online/off-line built-in self-test scheme for RAMs with ECC

Author

Lu, Hsing-Chen ; Li, Jin-Fu

Author_Institution

Dept. of Electr. Eng., Nat. Central Univ., Jhongli, Taiwan

fYear

2009

fDate

24-27 May 2009

Firstpage

1997

Lastpage

2000

Abstract

Embedded memory plays an important role in modern system-on-chip designs. However, the reliability issue of embedded memories becomes more and more critical with the shrinking of transistor feature size. This paper proposes a programmable online/off-line built-in self-test (BIST) scheme for random access memories (RAMs) with error correction code (ECC). The BIST scheme can be used for performing production testing and periodic transparent testing. In comparison with an existing transparent BIST scheme, the proposed BIST scheme does not incur the aliasing problem. Also, it can provide good fault location capability in online test mode. Experimental results show that the area cost of the proposed online/off-line BIST scheme is low-only about 2.6% for a 4Ktimes39-bit SRAM.

Keywords

SRAM chips; built-in self test; circuit reliability; circuit testing; error correction codes; fault location; RAM; SRAM; embedded memory; error correction code; fault location capability; off-line built-in self-test scheme; periodic transparent testing; production testing; programmable online built-in self-test scheme; random access memories; system-on-chip design; transistor; Built-in self-test; Costs; Error correction codes; Fault location; Performance evaluation; Production; Random access memory; System-on-a-chip; Testing; Transistors;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2009. ISCAS 2009. IEEE International Symposium on

Conference_Location

Taipei

Print_ISBN

978-1-4244-3827-3

Electronic_ISBN

978-1-4244-3828-0

Type

conf

DOI

10.1109/ISCAS.2009.5118183

Filename

5118183