Arithmetic/logic blocks for fine-grained reconfigurable units

Processing performance of algorithms implemented on conventional processors or DSP can degrade when bit level operations are involved. This degradation is related to the characteristics of logic and arithmetic operators present inside the processors, that are optimized for word level operations. Different methods have been proposed for overcoming this problem. A very interesting method is based on the introduction of specific logic and arithmetic units, jointly to the conventional integer or floating-point units. Due to the great variability of the bit level operations that must be performed, a fixed structure unit is not very suitable for this application. This fact has suggested the introduction of units based on arrays of reconfigurable cells, as the RAM based look-up tables. In this paper an alternative reconfigurable cell, specialized for the realization of bit manipulating unit, is described and evaluated. The comparison results show that the proposed solution is very efficient in terms of number of transistors (or silicon area) if compared to a conventional approach based on look-up table.