Clock gating and clock enable for FPGA power reduction

Author

Oliver, Juan P. ; Curto, Juan ; Bouvier, Diego ; Ramos, Manuela ; Boemo, Eduardo

Author_Institution

Inst. de Ingemeria Electnca, Univ. de la Republica, Montevideo, Uruguay

fYear

2012

fDate

20-23 March 2012

Firstpage

1

Lastpage

5

Abstract

This paper presents experimental measurements of power consumption using different techniques to turn off part of a system and switch between active and standby modes. The main ideas analyzed are: clock gating, clock enable, and blocking inputs. The laboratory work is described, including the measurement setups and the benchmark circuits. Quantitative measurements in both a 65 nm CMOS Cyclone III and a 45 nm CMOS Spartan 6 FPGAs are presented. The selected circuits used as benchmarks are different type of multipliers. Results of power consumption in active and standby modes are presented and compared.

Keywords

CMOS digital integrated circuits; clocks; field programmable gate arrays; power consumption; 45 nm CMOS Spartan 6 FPGA; 65 nm CMOS Cyclone III FPGA; FPGA power reduction; active mode; benchmark circuit; blocking input; clock enable; clock gating; multiplier; power consumption; standby mode; Benchmark testing; CMOS integrated circuits; Clocks; Field programmable gate arrays; Power demand; clock-enable; clock-gating; low-power; power measurements;

fLanguage

English

Publisher

ieee

Conference_Titel

Programmable Logic (SPL), 2012 VIII Southern Conference on

Conference_Location

Bento Goncalves

Print_ISBN

978-1-4673-0184-8

Type

conf

DOI

10.1109/SPL.2012.6211782

Filename

6211782