A high performance and low memory bandwidth architecture for motion estimation targeting high definition digital videos

This work presents a high performance and low memory bandwidth hardware architecture based on the Full Search block matching algorithm for the motion estimation on high definition digital videos. The motion estimation is the most computational intensive module of the video encoder and it requires besides the high processing throughput, a very high bandwidth with the external memory. The presented architecture explores the parallelism to achieve high processing rates and it uses a memory hierarchy to reuse data, reducing the required bandwidth with external memory. The architecture was described in VHDL and synthesized in a Xilinx Virtex 4 FPGA, achieving an operation frequency of 292 MHz and processing more than 38 high definition 1080 frames (1920×1080 pixels) per second, surpassing the requirements for real time processing.