An integrated synchronization architecture for 802.11 WLAN systems

Author

Lin, Jui-Yuan

Author_Institution

Southern Taiwan Univ. of Technol., Tainan

fYear

2007

fDate

17-19 Oct. 2007

Firstpage

1011

Lastpage

1014

Abstract

In the paper, an integrated synchronization system for IEEE802.11 multimode wireless LAN (WLAN) has been developed, simulated, and synthesized. A symbol timing recovery for 802.11a/g OFDM systems and a maximum likelihood (ML) matched filter for 802.11 and 802.11b systems are implemented and integrated into a single processor. All of the operation modes are mapped onto a shared, regular, data path with minimal control logic and routing. The proposed architecture is implemented by UMC 0.18 mum CMOS 1p4m technology and shows its superior performance in hardware complexity (gate counts).

Keywords

CMOS integrated circuits; OFDM modulation; matched filters; maximum likelihood estimation; synchronisation; telecommunication network routing; wireless LAN; 802.11 multimode WLAN systems; OFDM systems; UMC CMOS; hardware complexity; integrated synchronization architecture; maximum likelihood matched filter; network routing; size 0.18 mum; symbol timing recovery; CMOS technology; Communication standards; Costs; Hardware; Interference; Matched filters; OFDM; Timing; Wireless LAN; Wireless communication;

fLanguage

English

Publisher

ieee

Conference_Titel

Communications and Information Technologies, 2007. ISCIT '07. International Symposium on

Conference_Location

Sydney,. NSW

Print_ISBN

978-1-4244-0976-1

Electronic_ISBN

978-1-4244-0977-8

Type

conf

DOI

10.1109/ISCIT.2007.4392164

Filename

4392164