Practical considerations on doughnut transistors design

For applications where speed is important and custom design is an option, doughnut transistors constitute an attractive alternative to standard topologies, efficiently reducing parasitic capacitances while keeping large W/L ratios. This paper explores the influence of the layout style on the chip performance. To this aim a two-stage op-amp where different types of doughnut layouts have been considered for the Input differential pair has been constructed and measured. Experimental results suggest better performance for circle-type layouts.