A high throughput configurable FFT processor for WLAN and WiMax protocols

This paper presents a Radix-2 Single-Path Delay Feedback (R2SDF) configurable processor to calculate 64/128/512/1024/2048-point Fast Fourier Transform (FFT). Such range of FFT input sequences allows for the realization of the widely used wireless protocols IEEE 802.11n (WLAN) and the IEEE 802.16 (WiMax). The presented R2SDF configurable processor, as well as a fully sequential configurable processor that uses a single radix-2 butterfly (FSSR2B), were synthesized into Cyclone III Altera FPGAs to allow for a comparison in terms of hardware resources and performance. The R2SDF processor required more FPGA resources than the FSSR2B processor, mostly in the datapath. However, the overhead in terms of memory bits and registers was moderate. On the other hand, simulation results showed that the R2SDF processor is able to compute the FFT for a 2048-point sequence in 180 ms, being almost five times faster than the FSSR2B processor. The average relative error was evaluated by comparing the results provided by the designed FFT processors to that obtained from a software implementation of the FFT algorithm.