Optimized design of ECL gates with a power constraint

A design strategy for the optimization of the propagation delay of emitter coupled logic (ECL) gates when a power constraint is present is discussed. The optimization is carried out in terms of bias currents when a maximum level of total current for each gate, much lower than the optimum one, is available. The proposed approach is independent of the process used, avoiding the trial-and-error approach based on time-consuming simulations. The proposed strategy is validated by SPICE simulations on a two input multiplexer, using a bipolar process whose npn transistor has a transition frequency f_T of 20 GHz.