DocumentCode
2260935
Title
Ladder network modeling for closed-form interconnect time delay determination
Author
Antonini, Giulio ; Fen, G.
Author_Institution
Dept. of Electr. Eng., L´´Aquila Univ., Italy
Volume
3
fYear
2005
fDate
28 Aug.-2 Sept. 2005
Abstract
This paper presents a new method for computing time delay of RC interconnects based on closed form polynomials. The accuracy of the proposed formulas is tested by comparison with Spice simulations and results available in literature.
Keywords
RC circuits; SPICE; delay circuits; integrated circuit interconnections; ladder networks; network synthesis; polynomial approximation; RC interconnects; Spice simulation; closed form polynomial; closed-form interconnect time delay; ladder network modeling; time delay computing; Analytical models; Circuit simulation; Conductors; Delay effects; Delay estimation; Integrated circuit interconnections; Multiconductor transmission lines; Polynomials; Transmission line theory; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuit Theory and Design, 2005. Proceedings of the 2005 European Conference on
Print_ISBN
0-7803-9066-0
Type
conf
DOI
10.1109/ECCTD.2005.1523103
Filename
1523103
Link To Document