Improved Implementation of Costas Loop for DQPSK Receivers Using FPGA

In this paper, an improved carrier synchronization scheme using Costas Loop is proposed for all digital DQPSK receivers. Compared with the classic Costas Loop, this new scheme not only eases the operating load, but also reduces almost 10% of thermal power dissipation. Moreover, as the design is adopted all digitally, this scheme doesn´t need analog devices and shorten the carrier recover time. Consequently, based on the Altera Cyclone series FPGA EP1C12Q240C8, this recovery loop is implemented and the improved hardware implementation scheme is presented in detail. Finally, all the testing results are provided, and they show that the scheme can be efficiently operated when the digital carrier frequency offset is up to 1.5 kHz.