Implementation of high-speed digit-serial LDI allpass filters

In this paper, the performance of high-speed digit-serial processing elements for recursive systems is studied. A 6th-order LDI allpass filter has been implemented using digit-serial arithmetics, where two implementation cases are studied. In Implementation Case I the digit-serial processing elements are realized using unfolding (Parhi, 1991), which is the most common design method in digit-serial processing, and in Case 2 processing elements that can be pipelined to the hit-level are utilized. The filter realizations are implemented using a 0.18 μm standard cell technology. The studied properties are throughput and current consumption. It is concluded that implementing the filters using processing elements that can be pipelined to the bit-level results in a higher throughput. This is, however, at the expense of significantly higher current consumption. The throughput is on average 44% higher for Implementation Case 2 compared to Implementation Case 1. The difference in current consumption is on average 72%.