DocumentCode
2261012
Title
Rapid and energy-efficient testing for embedded cores
Author
Han, Yinhe ; Hu, Yu ; Li, Huawei ; Li, Xiaowei ; Chandra, Anshuman
Author_Institution
Inst. of Comput. Technol., CAS, Beijing, China
fYear
2004
fDate
15-17 Nov. 2004
Firstpage
8
Lastpage
13
Abstract
Conventional serial connection of internal scan chains brings the power and time penalty. A parallel core wrapper design (pCWD) approach is presented in this paper for reducing test power and test application time. The pCWD utilizes overlapping scan slices to reduce the number of scan slices loading. Experimental results on d695 of ITC2002 benchmark demonstrated that, about 2× shift time and 20× test power reduction can be achieved.
Keywords
boundary scan testing; design for testability; integrated circuit design; integrated circuit testing; ITC2002 benchmark; d695; embedded cores; energy-efficient testing; overlapping scan slices; parallel core wrapper design; rapid testing; test application time; test power reduction; Benchmark testing; Circuit testing; Computers; Content addressable storage; Energy efficiency; Intellectual property; Logic testing; Reconfigurable logic; System-on-a-chip; Test data compression;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Symposium, 2004. 13th Asian
ISSN
1081-7735
Print_ISBN
0-7695-2235-1
Type
conf
DOI
10.1109/ATS.2004.72
Filename
1376528
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