Applying in education an FPGA-based methodology to prototype ASIC soft cores and test ICs

Brazilian government has been investing in microelectronics, especially in hardware education as a strategic factor. In the literature, FPGA-based methodologies have been widely used in hardware and embedded systems design teaching. However, these methodologies don´t take into account timing design constraints and an in-depth verification process, essential to understand physical issues, reduce non-recurrent engineering costs and fault risks. This paper presents a design methodology that integrates functionally verified ASIC soft cores into an FPGA. The main goal of this methodology is to create an FPGA environment to emulate such soft core, which is fully compatible to test the manufactured ASIC. As a result of applying this methodology in education, students can learn the fundamentals of hardware and its designs challenges, not only development, but also verification and physical implications.