DocumentCode :
2261084
Title :
Test power reduction with multiple capture orders
Author :
Lee, Kuen-Jong ; Hsu, Shaing-Jer ; Ho, Chia-Ming
Author_Institution :
Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan
fYear :
2004
fDate :
15-17 Nov. 2004
Firstpage :
26
Lastpage :
31
Abstract :
This paper proposes a method to reduce the excess power dissipation during scan testing. The proposed method divides a scan chain into a number of sub-chains, and enables only one sub-chain at a time for both the scan and capture operations. To efficiently deal with the data dependence problem during the capture cycles, we develop a multiple-capture-orders method to guarantee the full scan fault coverage. A test pattern generation procedure is developed to reduce the test application time and a test architecture based on a ring control structure is adopted which makes the test control very simple and requires very low area overhead. Experimental results for large ISCAS´89 benchmark circuits show that the proposed method can reduce average and peak power by 86.8% and 66.1% in average, respectively, when 8 sub-chains are used.
Keywords :
automatic test pattern generation; boundary scan testing; power consumption; ISCAS´89 benchmark circuits; data dependence problem; full scan fault coverage; low area overhead; multiple capture orders; power dissipation; ring control structure; scan testing; test application time reduction; test architecture; test control; test pattern generation; test power reduction; Benchmark testing; Circuit faults; Circuit testing; Design methodology; Energy consumption; Interleaved codes; Logic; Power dissipation; System-on-a-chip; Test pattern generators;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Test Symposium, 2004. 13th Asian
ISSN :
1081-7735
Print_ISBN :
0-7695-2235-1
Type :
conf
DOI :
10.1109/ATS.2004.82
Filename :
1376531
Link To Document :
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