Implementation of a fully pipelined BCD multiplier in FPGA

Author

Guardia, Carlos Eduardo Minchola

Author_Institution

Digital Syst. Lab., Univ. Autonoma de Madrid, Madrid, Spain

fYear

2012

fDate

20-23 March 2012

Firstpage

1

Lastpage

6

Abstract

Decimal multiplication is one of the most frequently used operations in financial, scientific, commercial and internet-based applications. This paper presents an efficient implementation of a fully pipelined decimal multiplier designed with Carry Save Addition and coded into a reduced group of BCD-4221. This design is based on multiplier operands recoded in Signed-Digit radix-10, a simplified partial products generator, and decimal adders. A variety of multipliers architectures are processed on a Virtex-6 FPGA device. Several assessments are carried out in various N by M multiplications and their respective synthesis results show slightly optimistic figures in terms of area and delay in regard to some previously published works.

Keywords

field programmable gate arrays; floating point arithmetic; multiplying circuits; pipeline arithmetic; FPGA; M multiplication; N multiplication; Virtex-6 FPGA device; carry save addition; decimal adder; fully pipelined BCD multiplier; fully pipelined decimal multiplier; multiplier operand; multipliers architecture; signed-digit radix-10; simplified partial products generator; Adders; Compressors; Delay; Encoding; Field programmable gate arrays; Table lookup; BCD; Computer Arithmetic; FPGA; decimal floating point; signed-digit radix-10;

fLanguage

English

Publisher

ieee

Conference_Titel

Programmable Logic (SPL), 2012 VIII Southern Conference on

Conference_Location

Bento Goncalves

Print_ISBN

978-1-4673-0184-8

Type

conf

DOI

10.1109/SPL.2012.6211806

Filename

6211806