Design and implementation of a fully digital 4FSK demodulator

In this paper a fully digital 4FSK demodulator for double-conversion superheterodyne pager receivers based on ERMES standard is proposed. The demodulator includes three major parts: frequency discriminator, symbol detector and clock recovery modules. The key point in this design is its implementation through a simple hardware by avoiding complex algorithms and expensive hardware such as multipliers and dividers. Low power consumption is another important factor that has been considered in system-level and hardware-level design. The system was designed in 0.6μm CMOS process and resulted in a module with only 5472 transistors. Its performance was tested by FPGA-emulated experiments and good agreement between measurement and simulation is observed.