DocumentCode :
2261374
Title :
An efficient low-overhead policy for constructing multiple scan-chains
Author :
Rau, Jiann-Chyi ; Lin, Ching-Hsiu ; Chang, Jun-Yi
Author_Institution :
Dept. of Electr. Eng., Tamkang Univ., Taipei, Taiwan
fYear :
2004
fDate :
15-17 Nov. 2004
Firstpage :
82
Lastpage :
87
Abstract :
In this paper, we present an efficient method for reducing the total length of the scan paths. The method appropriately assigns scan flip-flops into scan chains after these flip-flops being placed. We compare our proposed method with previous work based on pre-placement (PP), greedy (GR), and stable marriage (SM) assignment, and show that our method is superior to the previous approaches. We also perform our method on some of the ISCAS 89 benchmarks. The obtained results of our experiments indicate that our algorithm improves the scan chain lengths by 79%-96% and the CPU time almost increases linearly.
Keywords :
boundary scan testing; flip-flops; integrated logic circuits; logic CAD; ISCAS 89 benchmarks; efficient low-overhead policy; greedy assignment; multiple scan-chains; pre-placement assignment; scan chain lengths; scan chains; scan flip-flops; stable marriage assignment; Circuit testing; Design for testability; Design methodology; Flip-flops; Hardware; Logic testing; Optimization methods; Routing; Samarium; Wire;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Test Symposium, 2004. 13th Asian
ISSN :
1081-7735
Print_ISBN :
0-7695-2235-1
Type :
conf
DOI :
10.1109/ATS.2004.23
Filename :
1376540
Link To Document :
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