A tool for optimum design of analog cells with reduced variance

Author

Rodríguez-Macias, R. ; Rodríguez-Vázquez, A. ; Fernández, F.V. ; Huertas, J.L.

Author_Institution

Dept. de Diseno de Microelectronica, Centro Nacional de Microelectron., Sevilla, Spain

fYear

1993

fDate

16-18 Aug 1993

Firstpage

608

Abstract

An automatic design tool capable of achieving strict specifications goals and reduced variance is presented. The specifications can be classified by the designer according to their priority. The optimization is based on heuristic methods so that it avoids local minima and needs no knowledge about sizing. The tool is open, capable of acting over any topologies and specifications. Variance can also be reduced in the specifications that the designer chooses. Example designs on a CMOS Miller OTA and a folded cascode OTA prove the tool capability

Keywords

analogue integrated circuits; circuit CAD; circuit optimisation; integrated circuit design; CAD; CMOS Miller OTA; analog cells; automatic design tool; folded cascode OTA; heuristic methods; optimization; optimum design tool; specifications goals; variance reduction; Analog circuits; Application specific integrated circuits; Circuit optimization; Circuit simulation; Circuit topology; Cost function; Design optimization; Equations; Modems; Optimization methods;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1993., Proceedings of the 36th Midwest Symposium on

Conference_Location

Detroit, MI

Print_ISBN

0-7803-1760-2

Type

conf

DOI

10.1109/MWSCAS.1993.342972

Filename

342972