Title :
A new path delay test scheme based on path delay inertia
Author :
Chen, Chung Liang ; Lee, Chung Len ; Wu, Ming-Shae
Author_Institution :
Dept. of Electron. Eng., National Chiao Tung Univ., Hsin Chu, Taiwan
Abstract :
This paper proposes a new path delay test scheme based on path delay inertia. The scheme only applies pulses of specified widths, which are proportional to path delays, to paths-under-test. It is simple, eliminating the conventional two-pattern test for delay faults. Issues, such as sensitivity of applied pulse widths w.r.t. path delay, related with the scheme were studied and an experimental chip was implemented to demonstrate the scheme.
Keywords :
circuit analysis computing; delays; fault diagnosis; integrated circuit testing; logic testing; applied pulse widths wrt path delay; delay faults; path delay inertia; path delay test scheme; paths-under-test; Added delay; Circuit faults; Circuit testing; Delay effects; Delay estimation; Pulse inverters; Pulse width modulation inverters; Semiconductor device modeling; Space vector pulse width modulation; Timing;
Conference_Titel :
Test Symposium, 2004. 13th Asian
Print_ISBN :
0-7695-2235-1
DOI :
10.1109/ATS.2004.11
